
BEGIN syrup_{{ userlogic_name.lower() }}

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = {{ userlogic_name }}
OPTION LONG_DESC = IPcore of {{ userlogic_name }} generated by flipSyrup
OPTION HDL = VERILOG
OPTION RUN_NGCBUILD = FALSE
{%- if not single_clock %}
OPTION PLATGEN_SYSLEVEL_UPDATE_PROC = platgen_update
{% endif %}

## User logic Clock and Reset
PORT UCLK = "", DIR = I, SIGIS = CLK
PORT URESETN = "", DIR = I, SIGIS = RST

## Bus Interfaces
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER

## Generics for VHDL or Parameters for Verilog
PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_DATA_WIDTH = {{ ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXI

## Max number of write commands able to be issued without responses
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI

## Ports
PORT M_AXI_ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK
PORT M_AXI_ARESETN = ARESETN, BUS = M_AXI, DIR = I, SIGIS = RST
PORT M_AXI_AWID = AWID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0]
PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0]
PORT M_AXI_AWLEN = AWLEN, BUS = M_AXI, DIR = O, VEC = [7:0]
PORT M_AXI_AWSIZE = AWSIZE, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_AWBURST = AWBURST, BUS = M_AXI, DIR = O, VEC = [1:0]
PORT M_AXI_AWLOCK = AWLOCK, BUS = M_AXI, DIR = O #, VEC = [1:0]
PORT M_AXI_AWCACHE = AWCACHE, BUS = M_AXI, DIR = O, VEC = [3:0]
PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_AWQOS = AWQOS, BUS = M_AXI, DIR = O, VEC = [3:0]
PORT M_AXI_AWUSER = AWUSER, BUS = M_AXI, DIR = O, VEC = [C_M_AXI_AWUSER_WIDTH-1:0]
PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O
PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I
PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0]
PORT M_AXI_WLAST = WLAST, BUS = M_AXI, DIR = O
PORT M_AXI_WUSER = WUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_WUSER_WIDTH-1):0]
PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O
PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I
PORT M_AXI_BID = BID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0]
PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0]
PORT M_AXI_BUSER = BUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_BUSER_WIDTH-1):0]
PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I
PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O
PORT M_AXI_ARID = ARID, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0]
PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0]
PORT M_AXI_ARLEN = ARLEN, BUS = M_AXI, DIR = O, VEC = [7:0]
PORT M_AXI_ARSIZE = ARSIZE, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_ARBURST = ARBURST, BUS = M_AXI, DIR = O, VEC = [1:0]
PORT M_AXI_ARLOCK = ARLOCK, BUS = M_AXI, DIR = O, VEC = [1:0]
PORT M_AXI_ARCACHE = ARCACHE, BUS = M_AXI, DIR = O, VEC = [3:0]
PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_ARQOS = ARQOS, BUS = M_AXI, DIR = O, VEC = [3:0]
PORT M_AXI_ARUSER = ARUSER, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ARUSER_WIDTH-1):0]
PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O
PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I
PORT M_AXI_RID = RID, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_THREAD_ID_WIDTH-1):0]
PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0]
PORT M_AXI_RLAST = RLAST, BUS = M_AXI, DIR = I
PORT M_AXI_RUSER = RUSER, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_RUSER_WIDTH-1):0]
PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I
PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O

################################################################################
# User defined ports
################################################################################
{%- for param in mpd_parameters | sort(attribute=0) %}
PARAMETER {{ param[0] }} = {{ param[1] }}, DT = {{ param[2] }}
{%- endfor %}

{%- for port in mpd_ports | sort(attribute=0) %}
PORT {{ port[0] }} = "", DIR = {{ port[1] }}{% if port[2] != '' %}, VEC = {{ port[2] }}{% endif %}
{%- endfor %}

END
