
BEGIN pycoram_{{ userlogic_name.lower() }}

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = {{ userlogic_name }}
OPTION LONG_DESC = IPcore of {{ userlogic_name }} generated by PyCoRAM
OPTION HDL = VERILOG
OPTION RUN_NGCBUILD = FALSE
{%- if not single_clock %}
OPTION PLATGEN_SYSLEVEL_UPDATE_PROC = platgen_update
{% endif %}

## User logic Clock and Reset
PORT UCLK = "", DIR = I, SIGIS = CLK
PORT URESETN = "", DIR = I, SIGIS = RST

## Control Thread Clock and Reset
{%- for thread in threads | sort(attribute='name') %}
PORT {{ thread.name }}_CCLK = "", DIR = I, SIGIS = CLK
PORT {{ thread.name }}_CRESETN = "", DIR = I, SIGIS = RST
{%- endfor %}

## Bus Interfaces
{%- for thread in threads | sort(attribute='name') %}
{%- for memory in thread.memories | sort(attribute='name') %}
BUS_INTERFACE BUS = {{ thread.name }}_{{ memory.name }}_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
{%- endfor %}
{%- for instream in thread.instreams | sort(attribute='name') %}
BUS_INTERFACE BUS = {{ thread.name }}_{{ instream.name }}_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
{%- endfor %}
{%- for outstream in thread.outstreams | sort(attribute='name') %}
BUS_INTERFACE BUS = {{ thread.name }}_{{ outstream.name }}_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
{%- endfor %}
{%- for iochannel in thread.iochannels | sort(attribute='name') %}
BUS_INTERFACE BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
{%- endfor %}
{%- for ioregister in thread.ioregisters | sort(attribute='name') %}
BUS_INTERFACE BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
{%- endfor %}

{% for memory in thread.memories | sort(attribute='name') %}
## Generics for VHDL or Parameters for Verilog
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_THREADS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_THREAD_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_DATA_WIDTH = {{ memory.ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI

## Max number of write commands able to be issued without responses
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_READ = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_WRITE = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ memory.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ memory.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ memory.name }}_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ memory.name }}_AXI

## Ports
PORT {{ thread.name }}_{{ memory.name }}_AXI_ACLK = "", BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, SIGIS = CLK
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARESETN = ARESETN, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, SIGIS = RST
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWID = AWID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWADDR = AWADDR, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWLEN = AWLEN, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWSIZE = AWSIZE, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWBURST = AWBURST, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWLOCK = AWLOCK, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O #, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWCACHE = AWCACHE, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWPROT = AWPROT, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWQOS = AWQOS, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWUSER = AWUSER, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [C_{{ thread.name }}_{{ memory.name }}_AXI_AWUSER_WIDTH-1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWVALID = AWVALID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ memory.name }}_AXI_AWREADY = AWREADY, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_WDATA = WDATA, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_WSTRB = WSTRB, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [((C_{{ thread.name }}_{{ memory.name }}_AXI_DATA_WIDTH/8) -1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_WLAST = WLAST, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ memory.name }}_AXI_WUSER = WUSER, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_WUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_WVALID = WVALID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ memory.name }}_AXI_WREADY = WREADY, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_BID = BID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_BRESP = BRESP, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_BUSER = BUSER, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_BUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_BVALID = BVALID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_BREADY = BREADY, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARID = ARID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARADDR = ARADDR, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARLEN = ARLEN, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARSIZE = ARSIZE, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARBURST = ARBURST, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARLOCK = ARLOCK, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARCACHE = ARCACHE, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARPROT = ARPROT, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARQOS = ARQOS, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARUSER = ARUSER, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_ARUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARVALID = ARVALID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ memory.name }}_AXI_ARREADY = ARREADY, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_RID = RID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_RDATA = RDATA, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_RRESP = RRESP, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_RLAST = RLAST, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_RUSER = RUSER, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ memory.name }}_AXI_RUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ memory.name }}_AXI_RVALID = RVALID, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ memory.name }}_AXI_RREADY = RREADY, BUS = {{ thread.name }}_{{ memory.name }}_AXI, DIR = O
{% endfor %}


{% for instream in thread.instreams | sort(attribute='name') %}
## Generics for VHDL or Parameters for Verilog
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_THREADS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_THREAD_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_DATA_WIDTH = {{ instream.ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI

## Max number of write commands able to be issued without responses
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_READ = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_WRITE = 0, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ instream.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ instream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ instream.name }}_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ instream.name }}_AXI

## Ports
PORT {{ thread.name }}_{{ instream.name }}_AXI_ACLK = "", BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, SIGIS = CLK
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARESETN = ARESETN, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, SIGIS = RST
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWID = AWID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWADDR = AWADDR, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWLEN = AWLEN, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWSIZE = AWSIZE, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWBURST = AWBURST, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWLOCK = AWLOCK, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O #, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWCACHE = AWCACHE, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWPROT = AWPROT, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWQOS = AWQOS, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWUSER = AWUSER, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [C_{{ thread.name }}_{{ instream.name }}_AXI_AWUSER_WIDTH-1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWVALID = AWVALID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ instream.name }}_AXI_AWREADY = AWREADY, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_WDATA = WDATA, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_WSTRB = WSTRB, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [((C_{{ thread.name }}_{{ instream.name }}_AXI_DATA_WIDTH/8) -1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_WLAST = WLAST, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ instream.name }}_AXI_WUSER = WUSER, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_WUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_WVALID = WVALID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ instream.name }}_AXI_WREADY = WREADY, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_BID = BID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_BRESP = BRESP, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_BUSER = BUSER, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_BUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_BVALID = BVALID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_BREADY = BREADY, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARID = ARID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARADDR = ARADDR, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARLEN = ARLEN, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARSIZE = ARSIZE, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARBURST = ARBURST, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARLOCK = ARLOCK, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARCACHE = ARCACHE, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARPROT = ARPROT, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARQOS = ARQOS, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARUSER = ARUSER, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_ARUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARVALID = ARVALID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ instream.name }}_AXI_ARREADY = ARREADY, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_RID = RID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_RDATA = RDATA, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_RRESP = RRESP, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_RLAST = RLAST, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_RUSER = RUSER, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ instream.name }}_AXI_RUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ instream.name }}_AXI_RVALID = RVALID, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ instream.name }}_AXI_RREADY = RREADY, BUS = {{ thread.name }}_{{ instream.name }}_AXI, DIR = O
{% endfor %}


{% for outstream in thread.outstreams | sort(attribute='name') %}
## Generics for VHDL or Parameters for Verilog
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_THREADS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_THREAD_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_DATA_WIDTH = {{ outstream.ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI

## Max number of write commands able to be issued without responses
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_READ = 0, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_WRITE = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ outstream.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ outstream.name }}_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = {{ thread.name }}_{{ outstream.name }}_AXI

## Ports
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ACLK = "", BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, SIGIS = CLK
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARESETN = ARESETN, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, SIGIS = RST
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWID = AWID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWADDR = AWADDR, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWLEN = AWLEN, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWSIZE = AWSIZE, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWBURST = AWBURST, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWLOCK = AWLOCK, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O #, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWCACHE = AWCACHE, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWPROT = AWPROT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWQOS = AWQOS, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWUSER = AWUSER, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [C_{{ thread.name }}_{{ outstream.name }}_AXI_AWUSER_WIDTH-1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWVALID = AWVALID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ outstream.name }}_AXI_AWREADY = AWREADY, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WDATA = WDATA, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WSTRB = WSTRB, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [((C_{{ thread.name }}_{{ outstream.name }}_AXI_DATA_WIDTH/8) -1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WLAST = WLAST, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WUSER = WUSER, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_WUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WVALID = WVALID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ outstream.name }}_AXI_WREADY = WREADY, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_BID = BID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_BRESP = BRESP, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_BUSER = BUSER, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_BUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_BVALID = BVALID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_BREADY = BREADY, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARID = ARID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARADDR = ARADDR, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_ADDR_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARLEN = ARLEN, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [7:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARSIZE = ARSIZE, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARBURST = ARBURST, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARLOCK = ARLOCK, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARCACHE = ARCACHE, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARPROT = ARPROT, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [2:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARQOS = ARQOS, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [3:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARUSER = ARUSER, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_ARUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARVALID = ARVALID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ outstream.name }}_AXI_ARREADY = ARREADY, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RID = RID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_THREAD_ID_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RDATA = RDATA, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RRESP = RRESP, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RLAST = RLAST, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RUSER = RUSER, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ outstream.name }}_AXI_RUSER_WIDTH-1):0]
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RVALID = RVALID, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ outstream.name }}_AXI_RREADY = RREADY, BUS = {{ thread.name }}_{{ outstream.name }}_AXI, DIR = O
{% endfor %}

{% for iochannel in thread.iochannels | sort(attribute='name') %}
## Generics for VHDL or Parameters for Verilog
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
{%- endif %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_DATA_WIDTH = {{ iochannel.ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
{%- else %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
{%- endif %}
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI #,TYPE = NON_HDL 
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ iochannel.name }}_AXI
{%- endif %}
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES = 1, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG00_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG00_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG00_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG01_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG01_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG01_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG02_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG02_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG02_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG03_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG03_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ iochannel.name }}_AXI_RNG03_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ iochannel.name }}_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL

## Ports
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ACLK = "", BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, SIGIS = CLK
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARESETN = ARESETN, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, SIGIS = RST
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWID = AWID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWADDR = AWADDR, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ADDR_WIDTH-1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWLEN = AWLEN, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [7:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWSIZE = AWSIZE, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [2:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWBURST = AWBURST, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWLOCK = AWLOCK, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWCACHE = AWCACHE, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWPROT = AWPROT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [2:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWREGION = AWREGION, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWQOS = AWQOS, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWUSER = AWUSER, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [C_{{ thread.name }}_{{ iochannel.name }}_AXI_AWUSER_WIDTH-1:0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWVALID = AWVALID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_AWREADY = AWREADY, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WID = WID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH-1:0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WDATA = WDATA, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WSTRB = WSTRB, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [((C_{{ thread.name }}_{{ iochannel.name }}_AXI_DATA_WIDTH/8) -1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WLAST = WLAST, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WUSER = WUSER, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_WUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WVALID = WVALID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_WREADY = WREADY, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_BID = BID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_BRESP = BRESP, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [1:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_BUSER = BUSER, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_BUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_BVALID = BVALID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_BREADY = BREADY, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARID = ARID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARADDR = ARADDR, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ADDR_WIDTH-1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARLEN = ARLEN, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [7:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARSIZE = ARSIZE, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [2:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARBURST = ARBURST, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARLOCK = ARLOCK, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARCACHE = ARCACHE, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARPROT = ARPROT, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [2:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARREGION = ARREGION, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARQOS = ARQOS, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARUSER = ARUSER, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ARUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARVALID = ARVALID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_ARREADY = ARREADY, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RID = RID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RDATA = RDATA, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RRESP = RRESP, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [1:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RLAST = RLAST, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RUSER = RUSER, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ iochannel.name }}_AXI_RUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RVALID = RVALID, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ iochannel.name }}_AXI_RREADY = RREADY, BUS = {{ thread.name }}_{{ iochannel.name }}_AXI, DIR = I
{% endfor %}

{% for ioregister in thread.ioregisters | sort(attribute='name') %}
## Generics for VHDL or Parameters for Verilog
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
{%- endif %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_ADDR_WIDTH = {{ ext_addrwidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_DATA_WIDTH = {{ ioregister.ext_datawidth }}, DT = integer, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
{%- else %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
{%- endif %}
{%- if not lite %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI #,TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI #,TYPE = NON_HDL 
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_AWUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_ARUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_WUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_BUSER_WIDTH = 1, DT = integer, ASSIGNMENT = CONSTANT, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = {{ thread.name }}_{{ ioregister.name }}_AXI
{%- endif %}
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES = 1, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG00_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG00_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG00_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG01_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG01_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG01_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG02_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG02_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG02_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG03_HIGHADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG03_HIGHADDR = 0x00000000, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_{{ thread.name }}_{{ ioregister.name }}_AXI_RNG03_BASEADDR, ISVALID = (C_{{ thread.name }}_{{ ioregister.name }}_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL

## Ports
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ACLK = "", BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, SIGIS = CLK
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARESETN = ARESETN, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, SIGIS = RST
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWID = AWID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWADDR = AWADDR, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ADDR_WIDTH-1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWLEN = AWLEN, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [7:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWSIZE = AWSIZE, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [2:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWBURST = AWBURST, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWLOCK = AWLOCK, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWCACHE = AWCACHE, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWPROT = AWPROT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [2:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWREGION = AWREGION, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWQOS = AWQOS, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWUSER = AWUSER, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [C_{{ thread.name }}_{{ ioregister.name }}_AXI_AWUSER_WIDTH-1:0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWVALID = AWVALID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_AWREADY = AWREADY, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WID = WID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH-1:0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WDATA = WDATA, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WSTRB = WSTRB, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [((C_{{ thread.name }}_{{ ioregister.name }}_AXI_DATA_WIDTH/8) -1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WLAST = WLAST, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WUSER = WUSER, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_WUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WVALID = WVALID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_WREADY = WREADY, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_BID = BID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_BRESP = BRESP, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [1:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_BUSER = BUSER, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_BUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_BVALID = BVALID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_BREADY = BREADY, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARID = ARID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARADDR = ARADDR, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ADDR_WIDTH-1):0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARLEN = ARLEN, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [7:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARSIZE = ARSIZE, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [2:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARBURST = ARBURST, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARLOCK = ARLOCK, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [1:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARCACHE = ARCACHE, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARPROT = ARPROT, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [2:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARREGION = ARREGION, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARQOS = ARQOS, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [3:0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARUSER = ARUSER, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ARUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARVALID = ARVALID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_ARREADY = ARREADY, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RID = RID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_ID_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RDATA = RDATA, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_DATA_WIDTH-1):0]
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RRESP = RRESP, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [1:0]
{%- if not lite %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RLAST = RLAST, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RUSER = RUSER, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O, VEC = [(C_{{ thread.name }}_{{ ioregister.name }}_AXI_RUSER_WIDTH-1):0]
{%- endif %}
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RVALID = RVALID, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = O
PORT {{ thread.name }}_{{ ioregister.name }}_AXI_RREADY = RREADY, BUS = {{ thread.name }}_{{ ioregister.name }}_AXI, DIR = I
{% endfor %}

{%- endfor %}

################################################################################
# User defined ports
################################################################################
{%- for param in mpd_parameters | sort(attribute=0) %}
PARAMETER {{ param[0] }} = {{ param[1] }}, DT = {{ param[2] }}
{%- endfor %}

{%- for port in mpd_ports | sort(attribute=0) %}
PORT {{ port[0] }} = "", DIR = {{ port[1] }}{% if port[2] != '' %}, VEC = {{ port[2] }}{% endif %}
{%- endfor %}

END
